The present application relates to a semiconductor device and a method for fabricating the same.
In order to obtain a required capacitance in a limited area, a metal layer such as a titanium nitride (TiN) layer has been used as an electrode of a capacitor e.g., a storage node (SN)), and a metal-insulator-metal (MIM) capacitor having a three-dimensional structure such as a cylinder or concave structure.
FIGS. 1A and 1B illustrate a method for fabricating a storage node of a typical semiconductor device, and FIG. 2 is a micrographic view illustrating limitations of the typical semiconductor device.
Referring to FIG. 1A, a first interlayer insulation layer 12 having a first storage node contact plug 13 is formed over a substrate 11 where a predetermined structure is formed, and a second interlayer insulation layer 14 is formed over the first interlayer insulation layer 12.
A second storage node contact plug 15 penetrates the second interlayer insulation layer 14 to contact with a top surface of the first storage node contact plug 13.
An etch stop layer 16 and a separation insulation layer 17 are sequentially formed over the second interlayer insulation layer 14, and a storage node hole 18 is formed by sequentially etching the separation insulation 17 and the etch stop layer 16 in order to expose a top surface of the second storage node contact plug 15.
A barrier metal layer (not shown) is formed along a surface of the storage node hole 18, and a thermal treatment process is performed to form an ohmic contact layer 19 over the second storage node contact plug 15. A storage node 20 is formed in the storage node hole 18.
Referring to FIG. 1B, the remaining separation insulation layer 17 is removed through a wet dip-out process to form the storage node 20 having a cylindrical type.
However, when the first interlayer insulation layer 12, the second interlayer insulation layer 14, and the separation insulation layer 17 are formed of an oxide layer, the second interlayer insulation layer 14 under the storage node 20 is etched to penetrate the storage node 20 through a chemical etchant during a wet dip-out process, as indicated by “A” in FIGS. 1B and 2. Thus, a defect such as a bunker 21 can occur. This bunker 21 generates a bridge between adjacent storage nodes 20 to cause a dual bit failure. Due to the bunker 21, an electrical short circuit phenomenon occurs between a metal interconnection and the storage node 20 during a subsequent metal interconnection process, or defective patterns may be formed during a mask process for forming the metal interconnection.
Additionally, since the degree of integration in a semiconductor device is increasing, a cell area where a capacitor may be formed is reduced and thus an aspect ratio of the storage node 20 is increased to obtain a sufficient electrostatic capacity in a limited cell area. Since the storage node 20 with a high aspect ratio causes deterioration of step coverage during a subsequent dielectric formation process, a fabricating yield of a semiconductor device is decreased. To overcome the above-mentioned limitations, a method for forming the thin storage node 20 of less than 300 Å is provided, but if the thickness of the storage node 20 is reduced, limitations due to the bunker 21 become worse because a chemical etchant penetrates more easily during a wet dip-out process.